1. Technical Field
The present disclosure relates to a semiconductor device and a method for fabricating the same, and more particularly, to a semiconductor device comprising a wire pattern and a fabricating method thereof.
2. Description of the Related Art
For semiconductor device density enhancement, the multigate transistor has been suggested as one of the scaling technologies. A multi-channel active pattern (or silicon body) in a fin or nanowire shape is formed on a substrate, with gates formed on a surface of the multi-channel active pattern.
The multigate transistor allows easy scaling, as it uses a three-dimensional channel. Further, current control capability can be enhanced without increasing a gate length of the multigate transistor. Furthermore, it is possible to effectively suppress short channel effect (SCE) which is the phenomenon that the electric potential of the channel region is influenced by the drain voltage.